The present invention relates to a technology effective for application to a system for controlling writing and erasing effected on an electrically programmable erasable nonvolatile memory and a system for controlling a booster circuit. The present invention also relates to, for example, a technology effective for use in a flash memory capable of collectively erasing data in block units, and a microcomputer with the flash memory built therein.
A flash memory makes use of nonvolatile storage or memory elements comprising MOSFETs formed in a two-layer structure having control and floating gates. As a writing system employed in the flash memory, there have heretofore been known, a system using an FN tunnel phenomenon and a system using hot electrons. The system using the FN tunnel phenomenon is a system wherein a voltage is applied between a control gate and a substrate (or well region) or between the control gate and the source or drain to inject an electrical charge into the floating gate or discharge it therefrom by use of the FN tunnel phenomenon, thereby changing a threshold voltage. On the other hand, the system using the hot electrons is a system wherein a current is caused to flow between a source and a drain in a state in which a high voltage is applied to a control gate and hot electrons produced in a channel are injected into a floating gate, thereby changing a threshold voltage.
The FN tunnel-based writing system has an advantage in that since a write current is small, writing is allowed in word-line units like 128 bytes, for example, and hence batch writing can be performed. In the writing system using the hot electrons on the other hand, batch writing in word-line units is difficult because a write current increases, and hence the writing is carried out in units of one byte. Storage or memory elements at the adoption of the FN tunnel-based writing system are difficult in micro-fabrication from relationships with withstand voltages and are not improved in integration density or degree. Therefore, the hot electron-based writing system is advantageous over the FN tunnel-base writing system in terms of an increase in capacity.
Incidentally, even when either of the writing system is adopted, the erasing of data in the flash memory is often carried out in block units, i.e., simultaneously with respect to a plurality of sectors which share the use of a well region and a source line.
The present inventors have discussed in detail the technology of shortening the time required for writing in the flash memory which has adopted the hot electron-based writing system.
With a view toward performing control on writing and erasing of a flash memory in a microcomputer with the flash memory built-in (hereinafter called a xe2x80x9cmicon with a built-in flashxe2x80x9d), a system has heretofore been adopted wherein a CPU sets write and erase bits of a control register lying within a flash control circuit and starts writing or erasing, and when the CPU manages time according to a program and a suitable time has elapsed, the CPU releases the write and erase bits to thereby complete write and erase operations. In the above-described micon with the built-in flash, which has adopted the FN tunnel-based writing system for performing writing simultaneously in the form of one sector (e.g., 128 bytes) corresponding to word-line units, for example, even the above-described control system whose time management is performed by the CPU, was effective because the time required to apply a write voltage was sufficiently longer than an operating period or cycle of the CPU. Even in the case of a so-called single flash memory built-in packaged with a controller for performing write control or the like on a flash memory, the controller has performed similar time management.
However, in the micon with the built-in flash, which has adopted the hot electron-based writing system, write pulses must be applied to drains of memory cells in the sector being in selection as described above in order bit by bit or in 8-bit units. In this case, the width of each write pulse becomes very short as compared with the FN-tunnel system. Therefore, the CPU is difficult to accurately control such a short time except when the operating frequency of the CPU is sufficiently high. When a margin therefor is sufficiently ensured, a write time required becomes long and a high voltage is applied even to each non-selected memory cell, whereby a phenomenon called xe2x80x9cthreshold voltage-varying disturbxe2x80x9d is apt to occur. On the other hand, a problem arises in that when the margin for the write pulse width is reduced, a write failure occurs and hence the number of times that pulses are applied up to the completion of writing, increases, so that the total time required for the writing becomes long.
Further, a problem arises in that an overhead time attendant on communications between the CPU and each memory is also included in the time required.
In the system wherein the CPU or controller manages the write pulses even in the case of the single flash as well as the micon with the built-in flash, the CPU or the like determines an end time assuming the worst case in regard to the characteristic of each storage element and a source voltage. Therefore, a flash memory good in characteristic will often cause needless latency time.
Further, when it is desired to type diversification of products different in storage capacity of flash memories, products different in operating frequency thereof, products different in source voltage, etc. in the micon with the built-in flash and the single flash, a boosting time for a booster circuit for generating a write voltage used for the flash memory also changes with a change in product. Therefore, the system wherein the write pulses are managed by the CPU or the like as described above, was also accompanied by a problem that it needed to re-design the booster circuit for each type and take measures such as rightsizing for a CPU""s program correction and controller""s control, and the time required to develop a new product became long.
An object of the present invention is to provide a nonvolatile memory like a flash memory capable of shortening a total write time required, and a semiconductor device such as a microcomputer with the nonvolatile memory built therein.
Another object of the present invention is to make it possible to provide a nonvolatile memory like a flash memory capable of performing writing and erasing in a optimum time without taking measures such as the re-design of a booster circuit, rewriting or updating of a CPU""s program, etc. even in the case where internal booster circuits are different in boosting time due to the difference between specifications of storage capacities or the like, and a semiconductor device such as a microcomputer with the nonvolatile memory built therein.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be explained in brief as follows:
A nonvolatile memory like a flash memory having adopted a hot electron-based writing system, or a semiconductor device with the nonvolatile memory built therein is provided with a memory array having a plurality of nonvolatile memory elements which store data according to magnitudes of threshold voltages thereof, a booster circuit which generates a voltage applied to each of the nonvolatile memory elements upon writing or erasing of the data, a boosted voltage detecting circuit which detects the level of the voltage boosted by the booster circuit, a write/erase control circuit which starts the writing or erasing based on the detection of the voltage by the boosted voltage detecting circuit, a write/erase end detecting circuit which detects the completion of the writing or erasing started by the write/erase control circuit, and an end flag indicative of the completion of the writing or erasing started by the write/erase control circuit.
According to the above means, the writing or erasing is automatically advanced internally from the boosting and the completion thereof is notified by the flag upon its completion. Therefore, it is not necessary to control write or erase pulses or the like from outside. Even when internal booster circuits are different in boosting time due to the difference in specifications such as storage capacity, the writing or erasing can be carried out in an optimum time without re-designing the booster circuit and taking measures such as rightsizing for a CPU""s program correction or controller""s control, etc.
Preferably, a control register having control bits each indicative of an entry into an operation for the writing or erasing is provided. The booster circuit starts boosting according to each of the control bits set thereto. Thus, an operation corresponding to the set control bit is automatically started.
Further, there are provided a plurality of booster circuits which generate a plurality of voltages respectively applied to the nonvolatile memory elements upon writing or erasing of data, and a plurality of boosted voltage detecting circuits which respectively detect the levels of the voltages boosted by the plurality of booster circuits. The write/erase control circuit starts writing or erasing based on the result that the plurality of boosted voltage detecting circuits have detected that all the boosted voltages respectively have attained a predetermined level. Consequently, the following operation can be started in the shortest time without causing needless time after the completion of boosting.
Here, the write/erase end detecting circuit comprises, for example, a delay circuit which delays a signal detected by the boosted voltage detecting circuit, or a counter circuit or the like which counts a clock signal, based on the detected signal. Thus, the write/erase end detecting circuit can easily be implemented through the use of the known technology.
There is also provided a discharge circuit which discharges the voltage boosted by the booster circuit. The discharge circuit starts discharging based on a signal detected by the write/erase end detecting circuit. Thus, it is possible to start the discharge of the voltage of the booster circuit without causing needless time after the completion of the writing or erasing.
There is further provided a discharge end detecting circuit which detects that the output voltage of the booster circuit, which has been discharged by the discharge circuit, has reached a predetermined level. The end flag is set based on a signal detected by the discharge end detecting circuit. Thus, it is possible to immediately notify the perfect completion of the operation attendant to the writing or erasing to the outside.
There are still further provided a data register which holds write data therein, and a write control circuit which applies a write voltage to each of bit lines according to the write data held in the data register. When bits for the write data held in the data register are of a logic xe2x80x9c1xe2x80x9d (or logic xe2x80x9c0xe2x80x9d), the write control circuit skips the bits and sequentially applies the write voltage in association with each of bits indicative of the logic xe2x80x9c0xe2x80x9d (or logic xe2x80x9c1xe2x80x9d). The nonvolatile memory like the flash memory having adopted the hot electron-based writing system can shorten a total write time required.
Further, the time required to apply the write voltage is determined based on a clock signal and changed according to a change in the cycle of the clock signal. Thus, the change in the time required to apply the write voltage according to the characteristic or the like of each storage element makes it possible to complete the optimum writing in a short period of time. Further, the change in the time required to apply the write voltage can be realized by a simple method of changing the cycle of the clock signal.
There is still further provided a shift register which sequentially outputs the write voltage, based on the clock signal and the write data held in the data register. The write/erase end detecting circuit detects that a pulse has reached a final stage of the shift register, thereby judging the writing to be completed. It is thus possible to sequentially apply the write voltage to each of the plural storage elements. A peak current can be controlled or suppressed as compared with the system of simultaneously applying the write voltage. It is also possible to detect the completion of the writing with extreme ease.
There are still further provided a level shifter which supplies the boosted voltage generated by the booster circuit to each of the nonvolatile memory elements upon writing or erasing, and a level determining circuit which determines the level of the boosted voltage generated by the booster circuit. When the level determining circuit has determined that the boosted voltage has exceeded a predetermined level, the level determining circuit serves so as to select a source voltage applied to the level shifter. It is thus possible to avoid the application of a voltage greater than a withstand voltage to each element constituting the level shifter and relax or lighten up withstand conditions.
There is still further provided a second level determining circuit which determines the level of the boosted voltage generated by the booster circuit. The booster circuit comprises a charge pump including MOSFETs constituting the charge pump, which are formed in a plurality of well regions formed on the surface of a semiconductor substrate in the form of being divided into the high-voltage side and the low-voltage side. Further, the booster circuit is configured so as to select a bias voltage applied to the well region on the high-voltage side when the second level determining circuit determines that the boosted voltage has reached a predetermined level. Thus, it is possible to avoid a reduction in the efficiency of boosting due to an increase in threshold voltage of each MOSFET constituting the charge pump by a substrate effect.
There are still further provided a command register which holds a command code supplied from outside, and a sequence control circuit which performs write or erase control according to the command code set to the command register. The sequence control circuit sets the respective control bits of the control register in response to a predetermined signal outputted from an internal circuit and starts the operations of other internal circuits to which the control bits are set. Thus, a series of operations such as the writing and its verify, and the erasing and its verify, etc. can be advanced without receiving instructions issued from outside. Further, the sequence control circuit can be simplified in configuration and made easy in design.
A second invention of the present application is one wherein a nonvolatile memory having a plurality of nonvolatile memory elements which store data according to the magnitudes of threshold voltages thereof, a booster circuit which generates a voltage applied to each of the nonvolatile memory elements upon writing or erasing of the data, a boosted voltage detecting circuit which detects the level of the voltage boosted by the booster circuit, a write/erase control circuit which starts the writing or erasing based on the detection of the voltage by the boosted voltage detecting circuit, a write/erase end detecting circuit which detects the completion of the writing or erasing started by the write/erase control circuit, an end flag indicative of the completion of the writing or erasing started by the write/erase control circuit, a control register having control bits each indicative of an entry into an operation for the writing or erasing, and a control circuit for giving instructions as to any of the writing, erasing and reading to the nonvolatile memory according to the setting of the control bits of the control register are formed on one semiconductor chip as a semiconductor device.
According to the above means, the writing or erasing is automatically advanced internally from the boosting and the completion thereof is notified by the flag upon its completion. Therefore, it is not necessary to control write pulses or the like from outside. Even when internal booster circuits are different in boosting time due to the difference in specifications such as storage capacity, the writing or erasing can be carried out in an optimum time without taking measures such as re-designing of the booster circuit, the rewriting of each program of the control circuit, etc. There is also provided a control register having control bits each indicative of an entry into an operation for the writing or erasing. Therefore, the simple setting of a predetermined control bit of the control register by the control circuit allows the automatic start of an operation corresponding to the control bit, thereby making it possible to easily execute a desired operation.
Further, preferably, the control circuit reads the end flag to thereby detect that the operation for the nonvolatile memory has been completed, and sets the corresponding control bit of the control register to thereby provide the following instructions. Thus, the control circuit needs not manage a write time, an erase time, etc., and the load on the control circuit can be lightened.